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Logic optimization
Results: 335

#	Item
211	Microsoft Word - fpga061s-mishchenko1.doc Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2009-12-16 19:04:56 Digital electronics Electronic design And-inverter graph Field-programmable gate array Logic synthesis Static timing analysis Placement Logic optimization Propagation delay Electronic engineering Electronic design automation Formal methods
212	SAT-Based Complete Don’t-Care Computation for Network Optimization Alan Mishchenko and Robert K. Brayton Department of EECS University of California, Berkeley {alanmi, brayton}@eecs.berkeley.edu Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2004-12-03 17:46:16 Boolean algebra Electronic design automation Formal methods Bioinformatics Boolean network Logic Boolean satisfiability problem Circuit Model checking Theoretical computer science Applied mathematics Mathematics
213	BOOKS I NEED REVIEWED FOR SIGACT NEWS COLUMN Algorithms 1. Algorithmics of matching under preferences By Manlove. 2. Pearls of Funcational Algorithm Design by Bird. 3. Jewels of Stringology Text Algorithms by Maxime Croc Add to Reading List Source URL: www.cs.umd.edu Language: English - Date: 2015-01-12 11:18:13 Computer science Mathematical optimization Mathematics Logic Theoretical computer science ACM SIGACT Algorithm
214	Optimization of Multi-Valued Multi-Level Networks M. Gao, J-H. Jiang, Y. Jiang, Y. Li, A. Mishchenko, S. Sinha, T. Villa, and R. Brayton Electrical Engineering and Computer Sciences Dept. University of California, Ber Add to Reading List Source URL: www.bvsrc.org Language: English* - Date: 2004-06-17 16:08:02 Diagrams Model checking Many-valued logic Flip-flop Electronics Mathematics Mathematical logic Electronic engineering Binary decision diagram Boolean algebra
215	Annual ERCIM Workshop on Constraint Solving and Constraint Logic Programming (CSCLP[removed]April 2011 Kings Manor, University of York Programme of Events Tuesday 12th April Add to Reading List Source URL: csclp2011.cs.st-andrews.ac.uk Language: English - Date: 2011-04-11 08:39:34 Computing Constraint logic programming Logic programming Answer set programming Constraint satisfaction problem Constraint Mathematical optimization Constraint programming Software engineering Computer programming
216	SAT-Based Complete Don’t-Care Computation for Network Optimization Alan Mishchenko Department of EECS University of California, Berkeley [removed] Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2004-04-30 02:47:03 Boolean algebra Computing Formal methods Electronic design automation Boolean satisfiability problem Boolean network Model checking Canonical form Lookup table Theoretical computer science Logic Mathematics
217	Fast Heuristic Minimization of Exclusive-Sums-of-Products∗ Alan Mishchenko and Marek Perkowski Department of Electrical and Computer Engineering Portland State University, Portland, OR 97207, USA [alanmi,mperkows]@ee.p Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2001-07-16 02:56:52 Electronic design Electronic design automation Boolean algebra Logic optimization Karnaugh map Logic synthesis Minimisation Cube Electronic engineering Design Digital electronics
218	SAT-Based Logic Optimization and Resynthesis Alan Mishchenko Robert Brayton Jie-Hong Roland Jiang Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2007-04-23 22:32:02 Electronic design automation Boolean network Science Mathematics Design Diagrams Formal methods And-inverter graph
219	Global Delay Optimization using Structural Choices Abstract This paper presents a fast global method for delay optimization after technology mapping. Timing analysis is used to identify timing-critical areas in the mappe Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2008-09-11 21:52:58 Digital electronics Electrical circuits Diagrams And-inverter graph Field-programmable gate array Static timing analysis Propagation delay Logic synthesis Retiming Electronic engineering Electronic design automation Formal methods
220	Merging Nodes Under Sequential Observability Michael L. Case1,2 1 Victor N. Kravets3 Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2008-04-02 23:52:50 Electronic design automation Logic in computer science Theoretical computer science Scan chain Logic optimization And-inverter graph Combinational logic Retiming Algorithm Electronic engineering Formal methods Digital electronics

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